1. Field of the Invention
The present invention relates to a wiring designing method for a semiconductor integrated circuit, which can adjust a delay amount of a signal flowing through a signal line of a semiconductor integrated circuit. More particularly, the present invention relates to a design support system for a semiconductor integrated circuit, which carries out the wiring designing method.
2. Description of the Related Art
A semiconductor integrated circuit is designed 15 by using a design support system. The design support system supports a circuit design and a layout design. The design support system is composed of a computer equipped with a CAD (Computer Aided Design) tool and a database.
FIG. 1 shows the configuration of a conventional design support system for a semiconductor integrated circuit. This design support system 1 is provided with an automatic placement tool 11, an automatic routing tool 12, an RC extraction tool 13, a delay calculation tool 14, a timing analysis tool 15, a correction value calculation tool 16 and a timing correction tool 17. Those tools are controlled by a processor in a computer. The processor refers to a tool program and a database stored in the computer to operate.
FIG. 2 shows the wiring sample of the conventional semiconductor integrated circuit. This semiconductor integrated circuit 2 is provided with a first signal line 21, a second signal line 22 and a third signal line 23. A first inverter 24 and a second inverter 25 are inserted in the first signal line 21.
An input end 21i of the first signal line 21 is coupled to an output buffer (not shown). An input end 22i of the second signal line 22 and an input end 23i of the third signal line 23 are connected to output buffers (not shown), respectively.
A delay amount of a signal flowing through the first signal line 21 is influenced by capacitance formed by the first signal line 21 and a wiring substrate. The delay amount of the signal flowing through the first signal line 21 is varied by changing a drive ability (an output level) of the output buffer coupled to the first signal line 21. The delay amount of the signal flowing through the first signal line 21 can be adjusted by changing the drive ability of the output buffer or changing a line length L0 of the first signal line 21 and accordingly changing the capacitance.
A technique for correcting a delay amount of a signal flowing through a signal line is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 8-330934). This gazette discloses a technique for canceling the delay amount by using an advance signal in which a phase is more advanced than that of the signal flowing through the signal line and a delaying signal in which a phase is more delayed than that of the signal flowing through the signal line.
In order to change the drive ability of the output buffer, the output buffer has a magnification for a selectable drive ability. The number of selections is different for each output buffer. The magnification of the drive ability is represented by, for example, integer times such as xc3x971, xc3x972, xc3x974, . . . .
The magnification of the selectable drive ability is limited to the integer times, it brings about such a situation that a desirable delay amount can not be set. The change in the magnification of the drive ability of the output buffer causes an input capacitance of the output buffer to be changed, and thereby causes a delay amount of a signal line mounted at a former stage of a signal line to be changed. As mentioned above, the adjustment of a delay amount of a signal flowing through one signal line accordingly requires a re-adjustment of a delay amount of another signal line.
The change in a line length of a signal line naturally leads to a change in a placement position of a cell (a device group) to be coupled to the signal line on a chip. The cell exclusively occupies a placement area wider than that of the wiring, which results in the limitation on a placement position. An occurrence of a constraint on the line length of the signal line causes the matching between the line length and the placement position of the cell to be difficult.
The development in a fine fabrication technique makes an array interval between lines to be narrow. If the array interval between the lines is narrower, the capacitance formed by two signal lines adjacent to each other has influence on a delay amount. It is very difficult to design a wiring layout while carrying out the above-mentioned matching and also considering the capacitance between the two signal lines.
Therefore, an object of the present invention is to provide a wiring designing method for a semiconductor integrated circuit, which can adjust a capacitance formed by two signal lines adjacent to each other, and a delay amount of a signal flowing through a signal line.
Means for solving the above-mentioned problems are explained as follows. A number, a symbol and the like together with a parenthesis xe2x80x9c( )xe2x80x9d is given to a technical item appearing in the explanation. The number, the symbol and the like coincides with a reference number, a reference symbol and the like given to a technical item constituting at least one implementation or a plurality of embodiments among a plurality of implementations or a plurality of embodiments in the present invention, especially, a technical item illustrated in a drawing corresponding to the implementation or the embodiment. The reference number and the reference symbol clarify the correspondence and the relation between a technical item noted in a claim and the technical item in the implementation or the embodiment. The correspondence and the relation do not imply that the technical item noted in the claim is limited to the technical item in the implementation or the embodiment.
The wiring designing method for the semiconductor integrated circuit according to the present invention calculates a capacitance of a capacitor formed by a signal line (201) and adjacent lines (204, 205) adjacent to the signal line (201), and adjusts line lengths (L2, L3) of the adjacent lines (204, 205) based on the calculated capacitance.
Another wiring designing method for a semiconductor integrated circuit according to the present invention calculates a delay amount of a signal flowing through the signal line (201), and calculates a delay difference indicative of a difference between the calculated delay amount and a desirable delay amount, and then adjusts the line lengths of the adjacent lines (204, 205) based on the calculated delay difference.
Still another designing method for a semiconductor integrated circuit according to the present invention calculates a differential capacitance corresponding to the delay difference, and adjusts the line length based on the differential capacitance and a distributed capacitance rate of an adjacent line.
Still another designing method for a semiconductor integrated circuit according to the present invention determines a phase of a control signal supplied to the adjacent lines (204, 205), based on a direction of a phase shift of the signal flowing through the signal line (201).
In still another designing method for a semiconductor integrated circuit according to the present invention, when the direction of the phase sift indicates a phase delay of a signal flowing through the signal line (201), the control signal supplied to the adjacent lines (204, 205) is set to a fixed potential having no phase.
In still another designing method for a semiconductor integrated circuit according to the present invention, when the direction of the phase shift indicates a phase advance of the signal flowing through the signal line (201), the control signal supplied to the adjacent lines is set to a first control signal having the same phase as the signal flowing through the signal line (201).
In still another designing method for a semiconductor integrated circuit according to the present invention, when the direction of the phase shift indicates a phase delay of the signal flowing through the signal line (201), the control signal supplied to the adjacent lines (204, 205) is set to a second control signal having a phase opposite to the signal flowing through the signal line (201).
A design support system for a semiconductor integrated circuit according to the present invention is comprises a signal line (201), a routing tool (102) and timing adjustment tools (106, 107). The routing tool (102) wires adjacent lines (204, 205) whose output ends are opened, and located adjacently to the signal line (201). The timing adjustment tools (106, 107) determines line lengths of the adjacent lines (204, 205), based on a delay amount of a signal flowing through the signal line (201).
In another design support system for a semiconductor integrated circuit according to the present invention, the timing adjustment tools (106, 107) measure a delay amount of a signal flowing through the signal line (201), and calculate a delay difference indicative of a difference between the measured delay amount and a desirable delay amount, and then adjust the line length of the adjacent lines (204, 205) based on the calculated delay difference.
In still another design support system for a semiconductor integrated circuit according to the present invention, the timing adjustment tools (106, 107) calculate a differential capacitance corresponding to the delay difference, and adjust the line length of the adjacent lines (204, 205) by referring to the differential capacitance and a distributed capacitance rate of the adjacent line.
In still another design support system for a semiconductor integrated circuit according to the present invention, the timing adjustment tools (106, 107) determine a phase of a control signal supplied to the adjacent lines, based on a direction of a phase shift of the signal flowing through the signal line (201).
In still another design support system for a semiconductor integrated circuit according to the present invention, when the direction of the phase shift indicates a phase delay of a signal, the timing adjustment tools (106, 107) set the control signal supplied to the adjacent lines at a fixed potential having no phase.
In still another design support system for a semiconductor integrated circuit according to the present invention, when the direction of the phase shift indicates a phase advance of the signal flowing through the signal line (201), the timing adjustment tools (106, 107) set the control signal supplied to the adjacent lines at a first control signal having the same phase as the signal flowing through the signal line (201).
In still another design support system for a semiconductor integrated circuit according to the present invention, when the direction of the phase shift indicates a phase delay of the signal flowing through the signal line (201), the timing adjustment tools (106, 107) set the control signal supplied to the adjacent lines at a second control signal having a phase opposite to the signal flowing through the signal line (201).